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Aeonic Generate Digital PLL for multi-instance, core logic clocking
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0.8 to 25 MHz Intermediate-frequency amplifier
IFA consists of 4-stage amplifier with tunable gain, AGC system, linear output buffer for differential analog output, analog-digital converter for digital output and a detector of output level.
The amplifier has differential inputs and outputs, and consists of 4 stages. Gain is sequentially reduced from the last stage to the first stage. This method allows to keep a low noise figure in wide gain range.
The output voltage maintained by AGC system at differential load 200 Ohm:
- for sinusoidal signal is 200 mV (p-p);
- for noise signal is 480 mV (p-p).
The block is fabricated on AMS035 BiCMOS 0.35 um technology
The amplifier has differential inputs and outputs, and consists of 4 stages. Gain is sequentially reduced from the last stage to the first stage. This method allows to keep a low noise figure in wide gain range.
The output voltage maintained by AGC system at differential load 200 Ohm:
- for sinusoidal signal is 200 mV (p-p);
- for noise signal is 480 mV (p-p).
The block is fabricated on AMS035 BiCMOS 0.35 um technology
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