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Register File with low power retention mode and 3 speed options
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1.2V GPIO library designed for the SVID three-line interface.
The 1.2V GPIO library provides an open-drain bi-directional I/O driver designed for the SVID three-line interface. It is compliant with the Intel SVID specification.
This 5nm library is available in an inline flip chip implementation.
To design a functional I/O power domain with this cell, an additional library is required – 1.8V Support: Power. That library contains isolated analog I/O, and a full complement of power cells along with spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
This 5nm library is available in an inline flip chip implementation.
To design a functional I/O power domain with this cell, an additional library is required – 1.8V Support: Power. That library contains isolated analog I/O, and a full complement of power cells along with spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
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