English
You are here:
1.5G MIPI D-PHY in SMIC 130nm~28nm
The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specification for MIPI D-PHY rev1.1 with speeds up to 1.5 Gbps per lane in 0.11um G process node, this ACTT Design IP of MIPI D-PHY supports DSI/DSI-2 and CSI-2 protocols.
These IPs is a mixed-signal PHY consisting of a DSI D-PHY transmitter and a DSI D-PHY receiver. The PHY IP is designed to be robust under varying signal strength and noise conditions.
The PHY IP is part of the comprehensive ACTT Design IP portfolio comprised of high speed interface, memory, low power analog, and system IPs.
These IPs is a mixed-signal PHY consisting of a DSI D-PHY transmitter and a DSI D-PHY receiver. The PHY IP is designed to be robust under varying signal strength and noise conditions.
The PHY IP is part of the comprehensive ACTT Design IP portfolio comprised of high speed interface, memory, low power analog, and system IPs.
View 1.5G MIPI D-PHY in SMIC 130nm~28nm full description to...
- see the entire 1.5G MIPI D-PHY in SMIC 130nm~28nm datasheet
- get in contact with 1.5G MIPI D-PHY in SMIC 130nm~28nm Supplier