A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation. The GPIO cell set can be configured as input, output, open-source, or open-drain with an optional internal 60K ohm pullup or pull-down resistor. Cells for IO & core power & ground with built-in ESD circuitry are included. Digital cells for 25MHz, 75MHz, and 150MHz allow optimization across SSO currents & power. A 3.3V I2C open-drain (fail-safe) and a 3.3V analog cell with ESD protection are included. The library is enriched with feed-through, filler, transition and domain-break cells to allow for flexible pad ring construction while maintaining ESD robustness. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.