MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
1.8V/3.3V Tolerant Fail-Safe General Purpose IO (GPIO) (CDM5A/7A-ESD) - TSMC 6nm 6FF
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interface IP IP
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