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1 Gbps DDR LVDS transmitter
065TSMC_LVDS_05 includes signal pins (INp and INn) to transmit data, and control pin EN_TX to configure the state of the transmitter. There are other two internal pins (VREF_TX and IREF_TX) to get voltage reference and current reference. PAD_OUTp and PAD_OUTn are complementary outputs to connect to the bonding pads. The block conforms to TIA/EIA-644 LVDS standards without hysteresis.
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