1 Gbps DDR rail to rail LVDS receiver

LVDS_RX is LVDS receiver with rail to rail input range. The interface to the core logic includes the output signal pins (OUTp, OUTn) to receive data and the control pins (EN_RX, EN_RES) to configure the state of the receiver. EN_RES enables the on-chip 100 Ohm resistor. The VREF12 is input voltage reference. Pin IREF_RX to get current reference from receiver bias. PAD_INp and PAD_INn are complementary input to connect to the bonding pads.

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