1 Gbps Rail to Rail LVDS receiver

065TSMC_LVDS_08 is LVDS receiver with rail to rail input range. The interface to the core logic includes the output signal pins (OUTP, OUTN) to receive data and the control pin EN_RX to configure the state of the receiver. The VREF12 pin is input voltage reference. Pin IREF_RX to get current reference from receiver bias. PAD_INP and PAD_INN are complementary input to connect to the bonding pads. This LVDS receiver does not employ hysteresis, and therefore does not comply with the hysteresis requirement of the TIA and IEEE standards for LVDS differential signaling at the specified rates.

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