USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
10/25/40/100G Ethernet MAC
XGMAC is an all- RTL design to achieve the lowest possible latency, and is fully compliant with the IEEE802.3 specification. The FIFO application interface can be configured for either Xilinx or Altera.
XGMAC is easily integrated into high end FPGAs such as Virtex 6, 7 series (Xilinx) & Stratix, Arria (Altera).
The smooth integration of the XGMAC into your product is supported by reference designs, concise code documentation, and access to expert engineers.
View 10/25/40/100G Ethernet MAC full description to...
- see the entire 10/25/40/100G Ethernet MAC datasheet
- get in contact with 10/25/40/100G Ethernet MAC Supplier
Block Diagram of the 10/25/40/100G Ethernet MAC IP Core
![10/25/40/100G Ethernet MAC Block Diagam](http://www.design-reuse.com/sip/blockdiagram/35781/20220506124414-main-mac-1-1.jpg)