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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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10-Bit 100MS/s 1.8V 66mW ADC, CMOS 0.18µm
The nSAD_UM180M_1V8_AD10b100M is a 100MS/s, 9.5 ENOB, highspeed and low-power AD converter designed on the UMC 180 MM technology. Built around a fully differential proprietary time-enhanced pipeline converter and a digital error correction circuitry, it consumes 66mW on silicon, reaching an energy efficiency of 911fJ/conversion-step.
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Block Diagram of the 10-Bit 100MS/s 1.8V 66mW ADC, CMOS 0.18µm
10-Bit ADC in UMC 180nm IP
- A/D Converter IP, 10 bits, 40Msps, UMC 0.18um Mixed-Mode process
- D/A Converter IP, Dual channel 10 bits current-steering type, 44Msps Differential current Output, UMC 0.18um G2 process
- A/D Converter IP, 10 bits, 10Msps, UMC 0.18um G2 process
- A/D Converter IP, 10 bits, 40Msps, UMC 0.18um Logic/Mixed-Mode process
- A/D Converter IP, 10 bits, 1Msps, with 8-to-1 input MUX, UMC 0.18um G2 process
- A/D Converter IP, 10 bits, 80Msps, UMC 0.18um Logic/Mixed-Mode process