10 Gbps Ethernet MAC

As the leading provider of 10 Gbps Ethernet (10GbE) for FPGA devices, Altera offers the 10GbE MegaCore® function intellectual property (IP) core for building systems with very high throughput Ethernet connection. This 10GbE media access control (MAC) along with a XAUI (4 x 3.125 Gbps) PHY, 10GBASE-R (10.3125 Gbps) PHY, or 10GBASE-KR (Backplane Ethernet) PHY IP core enables an Altera® device to interface to an external 10GbE PHY device or optical transceiver module and, in turn, to a 10GbE network, or directly over Copper backplane to another Backplane Ethernet device.

You can implement the XAUI (4 x 3.125 Gbps) PHY interface in Altera FPGAs with 3.125 Gbps serial transceivers, the 10GBASE-R (10.3125 Gbps) PHY interface to XFI or SFP+ modules with Altera Stratix® IV GT, Stratix V (GX, GS, and GT), and Arria® V (GT, GZ, and ST) FPGA 10.3125 Gbps serial transceivers, and the 10GBASE-KR (10.3125 Gbps) PHY interface for Backplane Ethernet with Altera Stratix V and Arria V GZ FPGAs.

The 10GbE MAC IP supports single speed 10Gb operation, and the 1G/10GbE and 10/100M/1G/10GbE (10M-10GbE) multi-speed options which allow you to build a flexible Ethernet port to connect to 10GbE or multi-data rate 10/100/1000MbE or 1G/10GbE external devices, optical modules or copper PHY devices, or directly to a copper backplane. The full Ethernet interface can be implemented with Altera 10M-10GbE MAC and SGMII / 1000BASE-X / 10GBASE-R (10M-10GbE) PHY IP or with 10GBASE-KR PHY backplane Ethernet IP. 10M-10GbE PHY IP supports 10/100/1000Mb operation with SGMII interface. This solution is supported in Stratix V and Arria V GZ FPGAs.

10GbE MAC with 10GBASE-R PHY, and 10M-10GbE MAC with 10M-10GbE PHY support the IEEE 1588 v2 high accuracy and high precision time stamping option in hardware. This feature facilitates standards-based accurate time and frequency synchronization to a network grand master. The 10GbE 1588 feature is supported in Stratix V (GX, GT, GS) and Arria V (GT, GZ) FPGAs. The 10M-10GbE 1588 feature is supported in Stratix V and Arria V GZ FPGAs.

Figures 1, 2, and 3 illustrate examples of Altera 10GbE MAC in different Altera devices with XAUI, XFI/SFI, or XGMII interfaces, respectively.

Figure 1. 10GbE MAC in an Altera Device with XAUI Interface



Notes:

* SDR XGMII = single data rate (SDR) XGMII (72 bits at 156.25 Mbps)
* XAUI physical coding sublayer (PCS) is implemented in hard IP in Stratix IV (GX, GT), Stratix II GX, Arria II GX, and Cyclone® IV GX FPGAs, and implemented in soft IP in Stratix IV (GX and GT), Stratix V (GX, GS, and GT), Arria V, and Cyclone V FPGAs with serial transceivers
* Avalon® Streaming (Avalon-ST) interface single-clock FIFO use is optional
* Avalon Memory-Mapped (Avalon-MM) bridge is a Qsys component
Figure 2. 10GbE MAC in an Altera Device with XFI or SFI 10G Serial Transceiver

 

Notes:

* Some 10.3 Gbps SFI system channels may need EDC chip here
* 10GBASE-R PCS is implemented in soft IP in Stratix IV GT and Arria V (GT) FPGAs, but is implemented in hard IP for Stratix V (GX, GS, and GT) and Arria V GZ FPGAs
* Avalon-ST interface single-clock FIFO use is optional
* I2C Controller IP can be licensed from Altera IP partners
Figure 3. 10GbE MAC in an Altera Device with XGMII Parallel Interface

 

Notes:

* SDR XGMII = single Data Rate XGMII (72 bits at 156.25 Mbps)
* Avalon-ST interface single-clock FIFO use is optional

• see the entire 10 Gbps Ethernet MAC datasheet
• get in contact with 10 Gbps Ethernet MAC Supplier