10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR)
The 10 Gigabit Ethernet backpane PCS/PMA (10GBASE-KR) is a Xilinx LogiCORE™ which has an optional FEC (forward error correction) and/or auto-negotiation protocol and link training allowing ultimate flexibility in your solution. The IP provides a XGMII interface to a 10 Gigabit Ethernet MAC and implements a 10.3125 Gbps serial single channel PHY over a backplane. The demand for 10G Ethernet is being driven in the data center as internet data traffic continues to grow. LAN application include Storage Area Networking (SAN), aggregation of 1G Ethernet links, and switch to switch links in the data center, equipment room or in different buildings.
NOTE: For UltraScale+ device support, refer to the 10G/25G Ethernet Subsystem
View 10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR) full description to...
- see the entire 10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR) datasheet
- get in contact with 10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR) Supplier
Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC