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100~450MHz DDR DLL with 80 Phase Selection, SMIC0.1.3um
The AR531S13 is a low-jitter low power dual channel delay locked loop (DLL) design support for DDR application. It is featured with a wide output frequency range from 100MHz to 450MHz. The system generates precise signal delays that can be programmed from 0 to 360 degree of the reference cycle with 80 steps maximum slave adjustment option for each channel.
The system contains a single master and expandable slave blocks. The master block optimizes power dissipation and area usage. The slave block determines arbitrary signal generation with certain desired phase delay from a reference clock according to selected fraction. The device supports DDR memory interface for SOC integration.
The system contains a single master and expandable slave blocks. The master block optimizes power dissipation and area usage. The slave block determines arbitrary signal generation with certain desired phase delay from a reference clock according to selected fraction. The device supports DDR memory interface for SOC integration.
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