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10Gbps Multi-Protocol PHY IP
The first IP for PCIe 3.1 with L1 sub-states support
The PHY IP is designed to deliver high eye-margin at low power for backplane application. Numerous auto-calibrated circuits, programmable state machines throughout the design for PHY performance tuning, and the LC tank PLL provide a low-power optimum performance design. PCIe low-power states are also optimized to reduce total system power. All standard power states are supported. The Cadence IP is engineered to quickly and easily integrate into any SoC, and to connect seamlessly with a Cadence or third-party PIPE 4.0-compliant controller. The IP is silicon-proven in multiple process nodes and has been extensively validated with multiple hardware platforms. The Cadence 10Gbps Multi-Protocol PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, and system and peripheral IP
The PHY IP is designed to deliver high eye-margin at low power for backplane application. Numerous auto-calibrated circuits, programmable state machines throughout the design for PHY performance tuning, and the LC tank PLL provide a low-power optimum performance design. PCIe low-power states are also optimized to reduce total system power. All standard power states are supported. The Cadence IP is engineered to quickly and easily integrate into any SoC, and to connect seamlessly with a Cadence or third-party PIPE 4.0-compliant controller. The IP is silicon-proven in multiple process nodes and has been extensively validated with multiple hardware platforms. The Cadence 10Gbps Multi-Protocol PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, and system and peripheral IP
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Block Diagram of the 10Gbps Multi-Protocol PHY IP IP Core
PCIe 3.1 IP
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 4.0 Controller with AMBA AXI interface
- Configurable controllers for PCIe 3.1 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications