112G Ethernet PHY in TSMC (N7, N5, N3P)
in area, high in performance demonstrating zero BER in greater than 45dB channels, and powerefficient at less than 5pJ/bit.
The PHY supports the Pulse-Amplitude Modulation 4-Level (PAM-4) and NonReturn-to-Zero (NRZ) signaling to deliver up to 800G Ethernet. The configurable transmitter and DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The CCA algorithm provides a robust performance across voltage and temperature variations. The low jitter PLLs and multi-loop
clock and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and non-
destructive 2D eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates with the Synopsys Physical Coding Sublayer and Digital Controllers/Media Access Controller (MAC) IP solutions to reduce design time and to help designers achieve first-pass silicon success.
Combined with Synopsys’ routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis, Synopsys provides a comprehensive 112G Ethernet PHY solution for fast and reliable SoC integration
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