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112G-XSR Pam4 for TSMC 7nm FinFET CMOS
Accelerating multi-die, multi-chip SoC designs
The Cadence® 112Gbps Extra Short Reach (XSR) SerDes IP for TSMC 7nm consists of eight lanes operating at 112Gigabit per second using PAM4 modulation. This IP enables die-to-die or die-to-optical engine connectivities for extremely low power and compact footprint. 112G-XSR SerDes is an enabling technology for chiplet and systemin-package (SiP) applications, which allows SoC providers to deliver more customized solutions that offer higher performance and yields while also shortening development cycles and reducing costs through greater IP reuse. The 112G-XSR SerDes IP supports primary Ethernet data rates within +/- 200ppm. Each receiver includes clock-data-recovery (CDR) for tracking PPM offset. An integrated micro-controller allows for fully autonomous startup, adaptation, and service operation without requiring ASIC intervention. A programming and observation interface is provided via a parallel bus with MDIO-style addressing (port, device, address). There are several comprehensive on-chip diagnostic tools that enable testability and easy debugging. A post-equalized histogram is available for accurate estimation of bit error rate (BER) even in the absence of actual bit errors. Vertical eye statistics can be logged to allow optional optimization of the device settings.
The Cadence® 112Gbps Extra Short Reach (XSR) SerDes IP for TSMC 7nm consists of eight lanes operating at 112Gigabit per second using PAM4 modulation. This IP enables die-to-die or die-to-optical engine connectivities for extremely low power and compact footprint. 112G-XSR SerDes is an enabling technology for chiplet and systemin-package (SiP) applications, which allows SoC providers to deliver more customized solutions that offer higher performance and yields while also shortening development cycles and reducing costs through greater IP reuse. The 112G-XSR SerDes IP supports primary Ethernet data rates within +/- 200ppm. Each receiver includes clock-data-recovery (CDR) for tracking PPM offset. An integrated micro-controller allows for fully autonomous startup, adaptation, and service operation without requiring ASIC intervention. A programming and observation interface is provided via a parallel bus with MDIO-style addressing (port, device, address). There are several comprehensive on-chip diagnostic tools that enable testability and easy debugging. A post-equalized histogram is available for accurate estimation of bit error rate (BER) even in the absence of actual bit errors. Vertical eye statistics can be logged to allow optional optimization of the device settings.
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