English
You are here:
112Gb/s PAM4 SERDES PHY 14nm
The Ethernet PHY IP is used for CEI-112G applications and serializes 8b/10b encoded data for Gen1 and Gen2, as well as 128b/130b encoded data for Gen3 and Gen4 during transmission, while de-serializing received code groups.
View 112Gb/s PAM4 SERDES PHY 14nm full description to...
- see the entire 112Gb/s PAM4 SERDES PHY 14nm datasheet
- get in contact with 112Gb/s PAM4 SERDES PHY 14nm Supplier
Block Diagram of the 112Gb/s PAM4 SERDES PHY 14nm
SERDES IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Low-Latency SerDes PMA - 10GbE, 25GbE
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency