English
You are here:
12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 40LL
The multi-protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support of PIPE
interface spec, Universal Serial Bus (USB) compliant with the USB 3.0, USB 2.0 (USB High-speed and Full speed) and Serial ATA (SATA) compliant with SATA 3.0 Specification. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.
interface spec, Universal Serial Bus (USB) compliant with the USB 3.0, USB 2.0 (USB High-speed and Full speed) and Serial ATA (SATA) compliant with SATA 3.0 Specification. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.
View 12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 40LL full description to...
- see the entire 12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 40LL datasheet
- get in contact with 12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 40LL Supplier
1.25 IP
- TSMC 12FFC Lane-based 1.25 - 22.5 Gbps Enterprise Multi-Standard SerDes
- 1.25 Gbps Four-Channel (4CH) LVDS Serializer with Pre-emphasis
- 1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
- 1.25 Gbps EPON SerDes IP
- Quad 1.06/1.25/2.125/1.56/2.5/3.125 Gbps Backplane SerDes
- Serial GMII 1.25 Gbps Phy