12.5G Multiprotocol Serdes IP, Silicon Proven in UMC 28HPC

The multi-protocol SerDes PHY consists of Serial ATA (SATA) conforming with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support for PIPE interface spec, Universal Serial Bus (USB) compliant with USB 3.0, USB 2.0 (USB Highspeed and Full speed), and USB 3.0 compliant with USB 3.0. Due to the provision of extra PLL control, reference clock control, and integrated power gating control, lower power consumption is obtained.
Additionally, because the aforementioned low power mode option is customizable, the PHY is extensively useful for a variety of situations with diverse power consumption considerations.

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