12-bit 1M Differential Rail to Rail SAR ADC

The analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The ADC includes a core internal SAR ADC, 8-1 MUX and touch screen drivers. The internal SAR ADC includes sample/hold circuits, a capacitive DAC, a comparator and logic control circuits. An external reference voltage is needed. In addition, the voltage reference input will be adjusted to allow encoding smaller analog voltage spanning to the full 12 bits of resolution. The ADC has dual speed modes - high speed and low speed - working in low speed mode could save some power. Moreover, it supports two running modes: free running and single running. In single running mode, SAR will switch to power down mode automatically so as to save power. The ADC is especially suitable to act as a Touch Screen Controller, demanding less off-chip components to complete the design. Battery voltage detect could be easily accomplished by the SAR ADC. It has a in-chip resistor divider. The converter is designed to allow operation with the NSC800 and INS8080A derivative control bus, with TRI-STATE output latches directly driving the data bus. The A/D appears like memory addresses or I/O ports to the microprocessor and no interfacing logic is needed. It is also suitable for integrated auxiliary codec applications and multi-converter architectures in wireless or battery-operated products.

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