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Aeonic Generate Digital PLL for multi-instance, core logic clocking
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14-bit 1-channel 40 to 160 MSPS pipeline ADC
065STM_ADC_01 is a high-speed 1-channel 14-bit ADC based on a pipelined architecture. The ADC consists of three main blocks: the ADC, RS, and the clock signal distribution block. For the correct operation of the ADC, the following characteristics are required: analog power supply 2.375 ÷ 2.625V (ADC_VDD, ADC_VDDA), digital power supply 2.375 ÷ 2.625V (ADC_VDDD), digital power supply 1.08 ÷ 1.32V (ADC_VDD12D); two reference currents 20uA (ADC_REF_i20u, ADC_i20u); reference bandgap voltage for the RS block 1.2V; differential clock input with a duty cycle of 45 ÷ 55%. The block has sampling rate range of 40 to 160 MSPS, which is controlled by the input clock ADC_CLKIP and ADC_CLKIN.
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