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400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
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14-bit 1-channel 50 MSPS pipeline ADC
The ADC has built on pipelined architecture. Pipelined ADCs consist of series-connected stages, each stage of the pipeline except the last, consists of parallel low-resolution ADC. This ADC is connected to the switched-capacitors DAC and an interstage residue amplifier (multiplying DAC). The amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. The output block aligns intermediate data in each stage, forms output code, and passes completed data to the output buffers.
The ADC consists of a reference currents and voltages circuit, LVDS clock receiver, ADC core and output logic. The ADC requires 1.62 ÷ 1.98 V analog supply and 0.9 ÷ 1.1 V, 1.62 ÷ 1.98 V digital supplies. The ADC supports standby mode which provides state with minimum power consumption.
The device is manufactured on TSMC 90 nm MS CMOS technology.
The ADC consists of a reference currents and voltages circuit, LVDS clock receiver, ADC core and output logic. The ADC requires 1.62 ÷ 1.98 V analog supply and 0.9 ÷ 1.1 V, 1.62 ÷ 1.98 V digital supplies. The ADC supports standby mode which provides state with minimum power consumption.
The device is manufactured on TSMC 90 nm MS CMOS technology.
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