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14b-10MSps Cal-SAR ADC
It is implemented with SAR architecture and offline calibration.
With 15mA total current consumption the Figure of merit of the ADC is 300 fJ/step, that is at the state of the art for its frequency sampling range.
The calibration time at maximum clockfrequency is less than 20 us.
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Block Diagram of the 14b-10MSps Cal-SAR ADC IP Core
14bits; 10Msps; SAR; ADC; IP
- A/D Converter IP, 10 bits, 10Msps, SAR type, Differential inputs, UMC 0.11um HS/AE process
- A/D Converter IP, 10 bits, 10Msps, SAR type, Differential inputs, UMC 0.11um HS/AE process
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