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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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17nA Current Bias with Enable - Low Voltage (1.0V), Ultra Low Power (90nW @ 1.8V) TowerJazz 0.18 μm
This macro-cell is a low power general purpose current bias generator core designed for TowerJazz 0.18µm TS18SL CMOS technology.
The circuit generates 2 × NMOS 17nA current branches. The current bias is temperature compensated. Output currents come from NMOS drain terminals, thus being sink-type sources.
The circuit generates 2 × NMOS 17nA current branches. The current bias is temperature compensated. Output currents come from NMOS drain terminals, thus being sink-type sources.
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Block Diagram of the 17nA Current Bias with Enable - Low Voltage (1.0V), Ultra Low Power (90nW @ 1.8V) TowerJazz 0.18 μm
Power Management IP
- Power Management Subsystem
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