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The core Implements a UDP/IP hardware protocol stack that enables wire-speed communication over a LAN or a point-to-point connection. It is ideal for offloading the host processor from the demanding task of UDP/IP and can be used in both FPGA and ASIC designs.
The core implements ARP request/reply supporting ARP cache and ICMP ping reply. The core includes a DHCP client module acquiring an IP address from external DHCP servers. The core supports V3 IGMP membership Query/Report messaging and multicast UDP traffic on both RX and TX.
The core provides the user logic with control and configuration interface of AXI4-Lite bus; five RX interfaces and five TX interfaces of AXI4 buses and AXI4-Stream buses. The core supports 32 RX channels and 32 TX channels.
The TX channels can be dynamically associated with any TX interface. The core supports VLAN, jumbo UDP packets with sizes up to 9K bytes, raw data interface and UDP port filters as well as TX UDP packet 32-bit counter on each TX port, RX UDP packet 32-bit counter on each RX port and RX error counters.
The core supports UDP checksum validation on RX and UDP checksum generation on TX as well as IP header checksum calculation and validation. They can be enabled and disabled through the control interface. The core is designed to well handle exceptions of internal memory exhaustion and invalid incoming packets while it is designed to make the max use of internal memory to effectively deal with the burst RX traffic and burst TX traffic.
A fully implemented reference design VHDL source code is included in the delivery. It aims to help users integrate the KMX 1G UDPIP core into their system more easily and more efficiently.
Simulation test bench VHDL source code with 36 test cases are included in the delivery.
1G UDP/IP Hardware Protocol Stack
The core Implements a UDP/IP hardware protocol stack that enables wire-speed communication over a LAN or a point-to-point connection. It is ideal for offloading the host processor from the demanding task of UDP/IP and can be used in both FPGA and ASIC designs.
The core implements ARP request/reply supporting ARP cache and ICMP ping reply. The core includes a DHCP client module acquiring an IP address from external DHCP servers. The core supports V3 IGMP membership Query/Report messaging and multicast UDP traffic on both RX and TX.
The core provides the user logic with control and configuration interface of AXI4-Lite bus; five RX interfaces and five TX interfaces of AXI4 buses and AXI4-Stream buses. The core supports 32 RX channels and 32 TX channels.
The TX channels can be dynamically associated with any TX interface. The core supports VLAN, jumbo UDP packets with sizes up to 9K bytes, raw data interface and UDP port filters as well as TX UDP packet 32-bit counter on each TX port, RX UDP packet 32-bit counter on each RX port and RX error counters.
The core supports UDP checksum validation on RX and UDP checksum generation on TX as well as IP header checksum calculation and validation. They can be enabled and disabled through the control interface. The core is designed to well handle exceptions of internal memory exhaustion and invalid incoming packets while it is designed to make the max use of internal memory to effectively deal with the burst RX traffic and burst TX traffic.
A fully implemented reference design VHDL source code is included in the delivery. It aims to help users integrate the KMX 1G UDPIP core into their system more easily and more efficiently.
Simulation test bench VHDL source code with 36 test cases are included in the delivery.
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