1KByte EEPROM IP with configuration 66p16w8bit
Write EEPROM data comes to input DI<7:0> and write process execute if signal WR=“1”.
Data DI<7:0>, page address ADR_P<6:0>, word address in page ADR_W<3:0> are latched into internal registers and cannot be changed until the end of the writing process. At the end of the writing, the READY = “1” flag is set.
Data reading is carried out by specifying the page address ADR_P<6:0> and the address of the word in the page ADR_W<3:0>. After applying the reading strobe, the DO<7:0> signal is set at the output corresponding to the reading data from the corresponding addresses of the EEPROM cell.
EEPROM also has a 7MHz gated clock cell output (glitchless start) from a built-in oscillator. The oscillator has frequency control inputs to compensate for process variation. Memory is optimized for usage in the industrial and commercial applications, requiring low power consumption and supply voltage.
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