MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
1Kbyte EEPROM with configuration 64p8w16bit
with volume 1 Kbyte (16(bit per word) x 8(words per page) x 64(pages)) with single-bit output data and parallel write data in one word.
Write EEPROM page data comes to input DI<15:0> and write process execute if signal WRITE = “1”.
Data DI<15:0>, page address ADR_P <5:0>, word address in page ADR_W <2:0> cannot be changed until the end of the writing process. Data reading is carried out by specifying the page address ADR_P <5:0> and the address of the word in the page ADR_W <2:0>, as well as the reading bit in the word ADR_B <3:0>. After applying the reading strobe, the DO signal is set at the output corresponding to the reading data from the corresponding addresses of the EEPROM cell. Memory is optimized for usage in the industrial and commercial applications, requiring low power consumption and supply voltage.
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