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Original Lossless codec IP core - Full HD 30fps@126MHz (1Sample/clk)
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2.8 Gbps LVDS IO
The LVDS I/O is a single macro (input, output and reference block). Both driver and receiver operating up to 1.4GHz (2.8 Gbps ). The Driver is designed to drive 100Ω differential termination.
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Block Diagram of the 2.8 Gbps LVDS IO IP Core
LVDS IP
- TSMC GF LVDS Tx/Rx with optional CMOS I/O
- TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link
- TSMC 3nm (N3E) 1.5V LVDS
- TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF