24-bit 1-channel 44.1 to 48kSPS delta-sigma ADC
Two second order feedforward modulators are used to create forth-order cascade 2-2 Sigma-Delta Modulator (Sigma-Delta ADC) with full differential signal processing. Each second order cascade utilizes a 3-level quantizer, so the output of each cascade is 1.5bit signal in signed binary code (-1, 0 and 1 output codes). In order to combine outputs of sigma-delta second order cascades and obtain output data stream, noise cancellation logic is used, which is implemented in digital section.
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