25G Ultra Low latency, 64-bit Ethernet MAC + PCS Solution (64-bit and 128-bit UI)
* Round Trip Latency of 59.6ns + Device Specific Transceiver Latency
As shown in the figure below, the 25Gbps Ethernet IP includes:
* Ultra-Low latency MAC; Tx = 17.4ns , Rx = 17.4ns; (64-bit user interface mode)
* Ultra-Low latency PCS; Tx = 12.4ns , Rx = 12.4ns; (64-bit user interface mode)
* Technology dependent transceiver wrapper for Altera and/or Xilinx FPGAs
* Statistics counter block (for RMON and MIB)
* MDIO and I2C cores for external module and optical module status/control
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Ethernet IP
- 10G-100G MACsec Security Module for Ethernet
- 224G Ethernet PHY in TSMC (N3E)
- 112G Ethernet PHY in TSMC (N7, N5, N3P)
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency