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DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC)
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25GE/10GE/SGMII/1000BASE-X and MAC
The fully integrated Physical Coding Sublayer (PCS), KR FEC (IEEE Clause 74 – fire code FEC), SGMII / 1000BASE-X and Media Access Controller (MAC) core for 25Gbps, 10Gbps, 2.5Gbps/1.25Gbps Ethernet applications is compliant with IEEE 802.3 standard and SGMII specification. The interface to the PMA supports a single channel Quad-mode bi-directional, serial interface. The PCS sublayer supports both 64/66B encoding (10GE) and 8B10B encoding (SGMII/1000BASE-X) with an optional FEC layer function for backplane (10G-KR) application. This Quad-Mode Core is configurable through software register.
The east-bound interface from the MAC provides a configurable 64-bit system interface.
The bound interface performs the mapping of transmit and receive data streams (at the PMA layer) to the on-chip SERDES.
The east-bound interface from the MAC provides a configurable 64-bit system interface.
The bound interface performs the mapping of transmit and receive data streams (at the PMA layer) to the on-chip SERDES.
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Block Diagram of the 25GE/10GE/SGMII/1000BASE-X and MAC
