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28n-TSMC Leakage Monitor
CT23302 provides means to determine the leakage current of some pre-defined MOS devices in the TSMC 28n technology node.
It is also possible to estimate the leakage process corner (fast or slow) of the IC die by comparing the measured values with a fixed table.
CT23302 is designed to have the capability of monitoring both core NMOS or PMOS process leakage current for the ultra-low Vt and standard Vt devices.
The Op-Amp integrator plus a comparator, translates the leakage current in a time value.
The digital logic controls the enable signals of the devices under test (DUT MOS) and the counter, which measures the time produced by the selected internal DUT.
The output result is a number inverse of the leakage current of the DUT.
It is also possible to estimate the leakage process corner (fast or slow) of the IC die by comparing the measured values with a fixed table.
CT23302 is designed to have the capability of monitoring both core NMOS or PMOS process leakage current for the ultra-low Vt and standard Vt devices.
The Op-Amp integrator plus a comparator, translates the leakage current in a time value.
The digital logic controls the enable signals of the devices under test (DUT MOS) and the counter, which measures the time produced by the selected internal DUT.
The output result is a number inverse of the leakage current of the DUT.
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Block Diagram of the 28n-TSMC Leakage Monitor IP Core
