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2D FIR Filter
The 2D FIR Filter IP core performs real-time 2D convolution of windowed portions of incoming video frames with coefficient matrices held in internal memory. Its flexible architecture supports a wide variety of filtering operations on various Lattice device families. The highly parameterized design takes advantage of the embedded DSP blocks available in Lattice FPGAs. A simple I/O handshake makes the core suitable for either streaming or bursty input video data. Coefficients may be set at compile time, or updated in system via a simple memory interface.
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Block Diagram of the 2D FIR Filter IP Core
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