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Unified Hardware IP for Post-Quantum Cryptography based on Kyber and Dilithium
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2D Scaler
The 2D Scaler IP core converts input video frames of one size to output video frames of a different size. Its flexible architecture supports a wide variety of scaling algorithms. The highly-configurable design takes advantage of the embedded DSP blocks available in Lattice FPGAs. A simple I/O handshake makes the core suitable for either streaming video or bursty input video data. In-system input and output frame size update is possible on a frame basis.
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Block Diagram of the 2D Scaler IP Core
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