3.125 Gbps DDR 1-channel CML transmitter

065TSMC_CML_02 core logic interface includes signal pins (INP1, INP2 and INN1, INN2) for data transmission, control pin EN_TX to configure transmitter state and control pin EN_PR to toggle pre-emphasis mode. Data on signal pins INP2 and INN2 should be one bit shifted (delayed) from that on INP1 and INN1 for pre-emphasis purposes. Differential CML output pins PAD_OUTP and PAD_OUTN should be connected to bonding pads.

• see the entire 3.125 Gbps DDR 1-channel CML transmitter datasheet
• get in contact with 3.125 Gbps DDR 1-channel CML transmitter Supplier