The ll_pllf0840s01_ln08lpp_306011 is a 1.8V/0.75V dual supply-voltage phase locked loop (PLL) for frequency synthesis. It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre-divider, a 10-bit main-divider, a 3-bit scaler, a delta-sigma modulator (DSM) and an automatic frequency control (AFC).
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3.93216GHz Fractional-N PLL
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Block Diagram of the 3.93216GHz Fractional-N PLL IP Core
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