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32-bit High Performance Single/Multicore RISC Processor
The CC100-C processor is a synthesisable Verilog model of a high performance 32-bit RISC processor. The model is highly configurable, and particularly suitable for system-on-a-chip (SoC) designs. The core is interfaced using the AMBA AHB, AHB-Lite and APB buses. The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.
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Block Diagram of the 32-bit High Performance Single/Multicore RISC Processor
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