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400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
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4.5GHz Fractional-N/SSC PLL
The ll_pllf0434s02_ln04lpp_3207002 is a 1.2V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis. It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre-divider, a 10-bit main-divider, a 3-bit scaler, a delta-sigma modulator (DSM) and an automatic frequency control (AFC).
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Block Diagram of the 4.5GHz Fractional-N/SSC PLL IP Core
