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40G/100G Ethernet Core
Xilinx 40G/100G Ethernet LogiCORE based on Sarance Technologies Best-In-Class Intellectual Property
Xilinx High-Speed Ethernet LogiCORE® (HSEC) is a high-performance and flexible implementation of the IEEE 802.32012 for 40Gbps and 100Gbps Ethernet. The HSEC implements the 40G and 100G aggregate Physical Coding Sublayer (PCS), and a 40G and 100G Media Access Controller (MAC) module. The HSEC is the world’s first implementation of the IEEE 802.32012 specifications and has been successfully deployed in a major ISP’s network in the USA. Xilinx also sells the CAUI and XLAUI PCS layers standalone with optional Auto_Negotiation and FEC for backplane applications. Xilinx 40G and 100G Ethernet LogiCORE is based on Sarance Technologies Intellectual Property and is delivered as a netlist implemented in UltraScale and Virtex® FPGA families.
Xilinx High-Speed Ethernet LogiCORE® (HSEC) is a high-performance and flexible implementation of the IEEE 802.32012 for 40Gbps and 100Gbps Ethernet. The HSEC implements the 40G and 100G aggregate Physical Coding Sublayer (PCS), and a 40G and 100G Media Access Controller (MAC) module. The HSEC is the world’s first implementation of the IEEE 802.32012 specifications and has been successfully deployed in a major ISP’s network in the USA. Xilinx also sells the CAUI and XLAUI PCS layers standalone with optional Auto_Negotiation and FEC for backplane applications. Xilinx 40G and 100G Ethernet LogiCORE is based on Sarance Technologies Intellectual Property and is delivered as a netlist implemented in UltraScale and Virtex® FPGA families.
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Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC