4K, 4:2:0/4:2:2:/4:4:4, 8/10/12 bit HEVC Decoder

HEVC video decoder IP core by ParaQum Technologies is an all-hardware, high performance video decoder which is easily integrable to complex FPGA based SoCs and supports upto 4K video decoding upto 60fos on Xilinx 7 series FPGAs. The core architecture is optimized for very low resource utilization. Coupled with low running frequencies, ParaQum HEVC Decoder IP core is ideal for deployment in mid-range FPGAs.

ParaQum HEVC decoder is world's first 4K real time HEVC decoder implemented on an FPGA with sub 150MHz clock frequencies.

High Efficiency Video coding (H.265) is the emerging video compression standard that promises 50% bit rate reduction compared to its predecessor H264. This IP core takes HEVC compliant elementary streams and outputs raw video. The decoder interfaces are AXI compliant for easy integration.

• see the entire 4K, 4:2:0/4:2:2:/4:4:4, 8/10/12 bit HEVC Decoder datasheet
• get in contact with 4K, 4:2:0/4:2:2:/4:4:4, 8/10/12 bit HEVC Decoder Supplier