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Aeonic Generate Digital PLL for multi-instance, core logic clocking
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5 MHz 14-bit 2 channel 300 kSPS cascade delta-sigma ADC
The block is fourth order cascade (2-2) delta-sigma ADC with 5-level quantizers in both stages. The block consists of:
- two delta-sigma modulators second order, coupled in series, in each channel
- clock generator
- bias current source
- voltage reference source
- CLA-, DWA-, BiDWA-correction of capacitors’ mismatch
- digital filter
ADC is designed for TSMC CMOS 65 nm technology using 6 levels of metal wiring.
- two delta-sigma modulators second order, coupled in series, in each channel
- clock generator
- bias current source
- voltage reference source
- CLA-, DWA-, BiDWA-correction of capacitors’ mismatch
- digital filter
ADC is designed for TSMC CMOS 65 nm technology using 6 levels of metal wiring.
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