50 - 800 MHz phase-locked loop

The synthesizer forms clock signal with frequency from 50 to 800 MHz. It consists of the ring VCO with frequency from 400 to 800 MHz, a programmable feedback divider, a low noise digital phase noise detector (PFD), a precision charge pump (CP) with internal loop filter and programmable clock divider to obtain a required output frequency. Output frequency is calculated by formula: FLO = (Fref*N)/(R*C). Power supply is 1.2V. Output signal is CMOS compatible.

• see the entire 50 - 800 MHz phase-locked loop datasheet
• get in contact with 50 - 800 MHz phase-locked loop Supplier