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50G Ethernet PCS/MAC/FEC
The fully integrated Physical Coding Sublayer (PCS) and Media Access Controller (MAC) core for 50Gbps Ethernet applications are compliant with IEEE 802.3cd draft standard. The interface to the PMA supports either 2x 25Gbps or a single 50Gbps bi-directional, serial interface. The PCS sublayer includes encoding, transcoding, scrambling, FEC layer, and symbol distribution.
The north-bound interface from the MAC provides a configurable n x 64-bit system interface.
The southbound interface performs the mapping of transmitting and receiving data streams (at the PMA layer) to the on-chip SERDES. This core is responsible for channel alignment and KP4 FEC management. The PCS supports an interface for 50GBASE-CR or 50GBASE-KR.
The north-bound interface from the MAC provides a configurable n x 64-bit system interface.
The southbound interface performs the mapping of transmitting and receiving data streams (at the PMA layer) to the on-chip SERDES. This core is responsible for channel alignment and KP4 FEC management. The PCS supports an interface for 50GBASE-CR or 50GBASE-KR.
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