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NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
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55LL general SP SRAM compiler with HVT bit cell.
55LL general SP SRAM compiler with HVT bit cell.
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Memories IP
- LPDDR5X DDR Memory Controller
- Duet Package of Embedded Memories and Logic Libraries for GF (55nm, 40nm, 22nm)
- Duet Package of Embedded Memories and Logic Libraries for Huali (55nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for SMIC (65nm, 40nm)
- Duet Package of Embedded Memories and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm, N7, N6, N5, N4P)
- Duet Package of Embedded Memories and Logic Libraries for UMC (40nm, 28nm)