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NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
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6.6GHz Fractional-N/SSC PLL
This PLL is a 1.8V/0.85V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis. It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre-divider, a 10-bit main-divider, a 3-bit scaler, a delta-sigma modulator (DSM) and an automatic frequency control (AFC).
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Block Diagram of the 6.6GHz Fractional-N/SSC PLL IP Core
