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6-bit, 5 GSPS Analog-to-Digital Converter IP block
The A6B5G is an ultra low-power, high-speed analog to digital converter (ADC) intellectual property (IP) block. It is a digitally folding, flash-type ADC, with a 6-bit resolution, and a sampling speed of 5 gigasamples per second (GSPS).
The A6B5G is a unique solution that provides the dual benefit of reaching an extremely high sampling speed while maintaining an exceptionally low power consumption of approximately 14 mW, making it a perfect fit for designs with high efficiency, low power and high performance requirements.
The cost-effective IP block has been designed and fabricated in the 28 nm CMOS FDSOI process and currently undergoing testing. The ADC IP is also available in a radiation-tolerant version for harsh environmental constraints.
The A6B5G is a unique solution that provides the dual benefit of reaching an extremely high sampling speed while maintaining an exceptionally low power consumption of approximately 14 mW, making it a perfect fit for designs with high efficiency, low power and high performance requirements.
The cost-effective IP block has been designed and fabricated in the 28 nm CMOS FDSOI process and currently undergoing testing. The ADC IP is also available in a radiation-tolerant version for harsh environmental constraints.
The A6B5G is a unique solution that provides the dual benefit of reaching an extremely high sampling speed while maintaining an exceptionally low power consumption of approximately 14 mW, making it a perfect fit for designs with high efficiency, low power and high performance requirements.
The cost-effective IP block has been designed and fabricated in the 28 nm CMOS FDSOI process and currently undergoing testing. The ADC IP is also available in a radiation-tolerant version for harsh environmental constraints.
The A6B5G is a unique solution that provides the dual benefit of reaching an extremely high sampling speed while maintaining an exceptionally low power consumption of approximately 14 mW, making it a perfect fit for designs with high efficiency, low power and high performance requirements.
The cost-effective IP block has been designed and fabricated in the 28 nm CMOS FDSOI process and currently undergoing testing. The ADC IP is also available in a radiation-tolerant version for harsh environmental constraints.
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