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NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
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6 track Ultra High Density standard cell library at TSMC 130 nm
TSMC 130 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest alternative to flip-flops).
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- see the entire 6 track Ultra High Density standard cell library at TSMC 130 nm datasheet
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standard cell IP
- Standard Cell Library in TSMC (12nm~180nm)
- Standard Cell Libraries - GLOBALFOUNDRIES 22FDX
- 7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V / 1.1 V)
- 9 track standard cell library at TSMC 55 nm
- 9 track standard cell library at TSMC 55 nm
- 6 track Ultra High Density standard cell library at TSMC 55 nm