MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
60 to 83 MHz High linearity intermediate frequency amplifier
Each stage of the amplifier has differential input and output. Gain is sequentially reduced from the buffer to the IFA first stage. Also gain can be set manually.
Frequency range is 60...83 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
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