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64-bit CPU Core with Level-2 Cache Controller
The 64-bit AX27L2 is a 5-stage processor that supports the latest RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instructions, “N” for user-level interrupts and Memory Management Unit (MMU) for Linux support.
AX27L2 features branch prediction, level-1 instruction and data caches, level-2 unified cache, local memories, ECC error protection, and Andes Custom Extension™ to add custom instructions to accelerate performance and reduce power consumption. In addition, it incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. AX27L2 also includes vectored and preemptive interrupts to serve diversified system events, AXI 128-bit bus, rich power management, and JTAG debug interface and trace interface for software development support.
AX27L2 features branch prediction, level-1 instruction and data caches, level-2 unified cache, local memories, ECC error protection, and Andes Custom Extension™ to add custom instructions to accelerate performance and reduce power consumption. In addition, it incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. AX27L2 also includes vectored and preemptive interrupts to serve diversified system events, AXI 128-bit bus, rich power management, and JTAG debug interface and trace interface for software development support.
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Block Diagram of the 64-bit CPU Core with Level-2 Cache Controller
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