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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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64-bit High performance Single Core Microprocessor
VEGA AS1161 features an out-of-order processing engine with a 16 stage pipeline enabling it to meet next gen computational requirements. The processor also supports single and double precision floating point instructions, and MMU for Linux based applications. AS1161 is optimized for high performance with integrated Instruction Cache, Data Cache and an advanced branch predictor enabling efficient branch execution. Features also include PLIC and vectored interrupts for serving various types of system events. An AXI or AHB interface enables ease of system integration and JTAG debug interface for development support.
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Block Diagram of the 64-bit High performance Single Core Microprocessor
Video Demo of the 64-bit High performance Single Core Microprocessor
VEGA Processor Introduction
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